CHAPTER 6 Architecting Testbenches 221 Reusable Verification Components 221 Procedural Interface 225 Development Process 226 Verilog Implementation 227 Packaging Bus-Functional Models 228 Utility... This description may be from another edition of this product.
Format:Hardcover
Language:English
ISBN:0792377664
ISBN13:9780792377665
Release Date:January 2000
Publisher:Secaucus, New Jersey, U.S.A.: Kluwer Academic Pub
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