Writing Testbenches: Functional Verification of Hdl Models

By Janick Bergeron

Book Overview

mental improvements during the same period. What is clearly needed in verification techniques and technology is the equivalent of a synthesis productivity breakthrough. In the second edition of Writing Testbenches, Bergeron raises the verification level of abstraction by introducing coverage-driven constrained-random transaction-level self-checking testbenches- all made possible through the introduction of hardware verification languages (HVLs), such as e from Verisity and OpenVera from Synopsys. The state-of-art methodologies described in Writing Test- benches will contribute greatly to the much-needed equivalent of a synthesis breakthrough in verification productivity. I not only highly recommend this book, but also I think it should be required reading by anyone involved in design and verification of today's ASIC, SoCs and systems. Harry Foster Chief Architect Verplex Systems, Inc. xviii Writing Testbenches: Functional Verification of HDL Models PREFACE If you survey hardware design groups, you will learn that between 60% and 80% of their effort is now dedicated to verification.

• Format: Paperback
• Language: English
• ISBN: 1461350123
• ISBN13: 9781461350125
• Release Date: October 2012
• Publisher: Springer
• Length: 478 Pages
• Weight: 1.56 lbs.
• Dimensions: 1.0" x 6.1" x 9.2"