Verilog(r) QuickStart

By James M. Lee

Book Overview

Welcome to the world of Verilog! Once you read this book, you will join the ranks of the many successful engineers who use Verilog. I have been using Verilog since 1986 and teaching Verilog since 1987. I have seen many different Verilog courses and many approaches to learning Verilog. This book generally follows the outline of the Verilog class that I teach at the University of California, Santa Cruz, Extension. This book does not take a "cookie-cutter" approach to learning Verilog, nor is it a completely theoretical book. Instead, what we will do is go through some of the formal Verilog syntax and definitions, and then show practical uses. Once we cover most of the constructs of the language, we will look at how style affects the constructs you choose while modeling your design. This is not a complete and exhaustive reference on Verilog. If you want a Verilog reference, I suggest one of the Open Verilog International (OVI) reference manuals.

• Format: Paperback
• Language: English
• ISBN: 146137801X
• ISBN13: 9781461378013
• Release Date: April 2013
• Publisher: Springer
• Length: 306 Pages
• Weight: 1.03 lbs.
• Dimensions: 0.7" x 6.1" x 9.2"

Customer Reviews

easy transition to verilog, good reference book

I have a VHDL background and this book was recommended to me. It made a smoooth transition into verilog. I read the book globally and then kept the book as a reference on my desk. If I needed something specific like file I/O and generating vectors, I used the example as a template to complete my verification. Also it helped to organize my files, like having one verification environment and easily plugging in tests by use of common tasks. Currently I am using Verilog and System Verilog, this book is still used regularly.

Very good book for beginer

I was lucky to have James Lee class at ucsc/ca. This book willbe very useful for all reader from beginer to practical expert.

Verilog testbench reference

The book provides a good resource for those designers that already know Verilog and wish to have coding tips for simulation testbenches. It is learn-by-example format, and is updated to include the '99 verilog standard. The book is well laid out, meaning that from the index it is easy to find a relevant coding example. I also bought "A designers guide to VHDL" Peter J. Ashendon which is a language reference for VHDL by example.