Verification Methodology Manual for Systemverilog

by Alan Hunter, Eduard Cerny, Janick Bergeron, et al.

Book Overview

Provides a reference methodology that can be adopted by designers and verification engineers for all types of System-on-a-Chip projects. With authors from ARM(R) and Synopsys(R), it combines ARM's expertise in the verification of complex, configurable IP from transaction-level SystemC to timing-critical register-transfer level (RTL) implementation, and Synopsys' strength in delivering an integrated RTL and system verification platform, including...

• Format: Paperback
• Language: English
• ISBN: 1461498139
• ISBN13: 9781461498131
• Release Date: December 2014
• Publisher: Springer
• Length: 503 Pages
• Weight: 1.60 lbs.
• Dimensions: 1.1" x 6.1" x 9.2"