Ultra Low Phase Noise PLL Frequency Synthesizer for Ku Band

Bys: Nikam, Shobha and Mane, Pradeep

Satellites are crucial in global communications, necessitating widespread transceiver use. Frequency bands, carefully chosen to prevent interference, employ Phase-Locked Loops (PLLs) as synthesizers. Designing a single-chip PLL for efficient frequency multiplication is vital in today's tech landscape. Literature reveals a gap in research for the Ku band (12-18 GHz), lacking single-chip, wideband PLLs. This work introduces a 12-18 GHz charge pump-based integer-N PLL, compact at 0.076mm , designed in 0.18μm CMOS technology using Cadence Virtuoso. Achieving exceptional phase noise performance (-122.83 dBc/Hz at 1 MHz offset), it fulfills satellite communication requirements with reduced PFD dead zones, negligible current mismatch, and impressive dynamic range. Lock-in range: 8.69 GHz, capture range: 5 MHz, demonstrating the feasibility of a fully integrated PLL chip for superior satellite applications.

• Format: Paperback
• Language: English
• ISBN: 6207450639
• ISBN13: 9786207450633
• Release Date: January 1
• Publisher: LAP Lambert Academic Publishing
• Length: 168 Pages
• Weight: 0.56 lbs.
• Dimensions: 0.4" x 6.0" x 9.0"