RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design

by Stuart Sutherland

Book Overview

This book is both a tutorial and a reference for engineers who use the SystemVerilog Hardware Description Language (HDL) to design ASICs and FPGAs. The book shows how to write SystemVerilog models at the Register Transfer Level (RTL) that simulate and synthesize correctly, with a focus on proper coding styles and best practices.SystemVerilog is the latest generation of the original Verilog language, and adds many important capabilities to efficiently...

• Format: Paperback
• Language: English
• ISBN: 1546776346
• ISBN13: 9781546776345
• Release Date: June 2017
• Publisher: Createspace Independent Publishing Platform
• Length: 488 Pages
• Weight: 1.50 lbs.
• Dimensions: 1.0" x 6.0" x 9.0"