Programming RISC-V Systems: Compilers, Kernels, and Bare-Metal Control

By Nova Trelix

RISC-V has moved from research curiosity to production reality, inviting systems engineers to shape hardware-software boundaries with unusual clarity. This book is written for experienced practitioners-kernel and firmware developers, compiler engineers, and performance-minded library authors-who need rigor rather than recipes. It closes the gap between specification and implementation, translating the unprivileged and privileged ISA into robust control over traps, interrupts, and memory, and guiding you from deterministic bare-metal bring-up to Linux-capable platforms without losing sight of performance, correctness, or debuggability.

You will master the psABI and calling conventions, ELF and linker relaxation, and GNU/LLVM pipelines tuned for RISC-V (GCC 13, Clang/LLVM 17). The text develops trap handling, CSR/Zicsr usage, and RVWMO/Ztso memory-model reasoning; implements Sv39/Sv48 paging, shootdowns, and PMP hardening; and builds production-grade startup paths and ECALL interfaces. It dissects the SBI and OpenSBI flow, Device Tree discipline, and Linux 6.8 specifics-boot, IRQs, syscalls, VDSO, drivers-then extends to QEMU 8 for deterministic experiments, GDB 14 and DWARF unwind for postmortem fidelity, perf/eBPF for system profiling, and virtualization patterns, culminating in cohesive case studies and reproducible builds.

Prerequisites include strong C and assembly, familiarity with OS internals and concurrency, and comfort with toolchains and ELF. The book's differentiator is its specification-aligned, production-focused treatment (Privileged 1.12, psABI v1.0) with verified tool versions, end-to-end build artifacts, and defensible ABI boundaries-practical depth for engineers who ship.

• Format: Paperback
• Language: English
• ISBN: B0FY1B41HB
• ISBN13: 9798271833908
• Release Date: October 2025
• Publisher: Independently Published
• Length: 386 Pages
• Weight: 1.13 lbs.
• Dimensions: 0.8" x 6.0" x 9.0"