Nano-CMOS and Post-CMOS Electronics: Devices and Modelling

The demand for ever smaller and portable electronic devices has driven metal oxide semiconductor-based (CMOS) technology to its physical limit with the smallest possible feature sizes. This presents various size-related problems such as high power leakage, low-reliability, and thermal effects, and is a limit on further miniaturization. To enable even smaller electronics, various nanodevices including carbon nanotube transistors, graphene transistors, tunnel transistors and memristors (collectively called post-CMOS devices) are emerging that could replace the traditional and ubiquitous silicon transistor. This book explores these nanoelectronics at the device level including modelling and design.

Topics covered include high-k dielectrics; high mobility n and p channels on gallium arsenide and silicon substrates using interfacial misfit dislocation arrays; anodic metal-insulator-metal (MIM) capacitors; graphene transistors; junction and doping free transistors; nanoscale gigh-k/metal-gate CMOS and FinFET based logic libraries; multiple-independent-gate nanowire transistors; carbon nanotubes for efficient power delivery; timing driven buffer insertion for carbon nanotube interconnects; memristor modeling; and neuromorphic devices and circuits.

This book is essential reading for researchers, research-focused industry designers/developers, and advanced students working on next-generation electronic devices and circuits.

• Format: Hardcover
• Language: English
• ISBN: 1849199973
• ISBN13: 9781849199971
• Release Date: April 2016
• Publisher: Institution of Engineering & Technology
• Length: 384 Pages
• Weight: 1.50 lbs.
• Dimensions: 1.0" x 6.3" x 9.5"