Introduction.- Reconfigurable Real-Time Memory Controller Architecture.- Memory Patterns.- Cycle-Accurate SDRAM Power Modeling.- Power/Performance Trade-Offs.- Conservative Open-Page Policy.- Reconfiguration.- Related Work.- Conclusions and Future Work.- Appendix A: ILP Problem Formation.- Appendix B: Memory Specifications.- Appendix C: Code Listings.- Appendix D: List of Acronyms.- Appendix E: List of Symbols.