High-Level Estimation and Exploration of Reliability for Multi-Processor System-On-Chip

By Anupam Chattopadhyay and Zheng Wang

Book Overview

This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.

• Format: Hardcover
• Language: English
• ISBN: 9811010722
• ISBN13: 9789811010729
• Release Date: July 2017
• Publisher: Springer
• Length: 197 Pages
• Weight: 1.07 lbs.
• Dimensions: 0.6" x 6.1" x 9.2"