ESD Industry Council System Level White Paper III Archive: Common Misconceptions and System Efficient ESD Design Recommendations

By Charvaka Duvurry and Harald Gossner

Over the last twenty years, an increasing misconception between system level designers (OEMs) and semiconductor component (IC) providers has become very apparent relating to three specific ESD issues:

ESD test specification requirements of system vs. IC providers;Understanding of ESD failures in terms of physical failure and system upset and what causes these failures in terms of system level and IC level constraints;Lack of acknowledged responsibility between system designers and IC providers regarding proper system level ESD design.

In White Paper 1 from the Industry Council on ESD Target Levels, which presented a paradigm shift in the realistic and safe IC level ESD requirements, we introduced the importance of separately addressing the system specific and IC specific ESD issues. In White Paper 3 we present the first comprehensive analysis of system ESD understanding including ESD related system failures, and design for system robustness. The main purpose of the present document is to close the existing communication gap between the OEMs and IC providers by involving the expertise from OEMs and system design experts. This will be accomplished by what we describe in this document as "System-Efficient ESD Design" (SEED) which promotes a common IC / OEM understanding of the correct system level ESD needs. White paper 3 will be constructed of two parts. A key finding of Part I of the white paper is the development of a framework for sharing IC / system level circuit information so that best practice ESD protection and controls can be co-developed and properly shared.

Later, in Part II of White Paper 3, the Industry Council will use the information in Part I to establish recommendations for IC and system level manufacturers regarding proper protection, proper controls and best practice ESD tests, which can properly assess ESD and related EMI performance of system level tests. The purpose of White Paper 3, Part II will be to better define the ESD relationship between IC manufacturers and system level OEMs and their respectiveresponsibilities.

• Format: Paperback
• Language: English
• ISBN: 1958367117
• ISBN13: 9781958367117
• Release Date: October 2023
• Publisher: Pragma Media
• Length: 412 Pages
• Weight: 2.09 lbs.
• Dimensions: 0.8" x 8.5" x 11.0"