Designing Digital Systems With SystemVerilog (v3.0)

By Brent E. Nelson

This was written as an introductory textbook on digital logic design and the SystemVerilog language. The structure of the book makes it useful as both a way to learn digital design, a way to learn SystemVerilog, or a way to learn both. It is targeted at University level courses or at practicing engineers who desire to learn these topics. This book (and its previous versions) have been used for nearly 20 years at Brigham Young University and other places as a textbook for courses on digital systems design. The text chapters are listed below. The chapters are short and concise, typically covering one lecture's worth of material (in the case of courses at Brigham Young University). Roughly 1/3 of the chapters focus on SystemVerilog, each one targeted at teaching how to implement the immediately preceding chapters' digital circuit design concepts using HDL. Additionally, a full chapter on SystemVerilog testbenches for verifying designs is included. The book starts with Boolean Logic and combinational logic design and then moves on to storage elements (flips flops) and sequential circuit design and finite state machine-based design. As can be seen, the SystemVerilog chapters are intermixed through the text but could be covered later than they appear. Introduction Number Systems and Binary Encodings Signed Number Representations, Negation, and Arithmetic Boolean Algebra and Truth Tables Logic Gates Boolean Algebra - Part II Gates - Part II An Introduction to Gate-Level Design Using SystemVerilog Gate-Level Arithmetic Higher Level Building Blocks: Multiplexers Continuing on With SystemVerilog - Hierarchical Design, Constants, and Multi-Bit Signals Karnaugh Maps - Optional Material Gate Delays and Timing in Combinational Circuits Dataflow SystemVerilog Latches and Flip Flops Registers and RTL-Based Design Behavioral SystemVerilog for Registers Behavioral SystemVerilog for Combinational Logic Memories Implementation of Simple Sequential Circuits: IFL, OFL, and Timing State Graphs Finite State Machines State Machine Design Using SystemVerilog Handling Asynchronous Inputs and Generating Glitch-Free Outputs Field Programmable Gate Arrays (FPGAs) - An Introduction Case Study - Debouncing Switches and Detecting Edges Writing Testbenches in SystemVerilog Case Study: The Design of a UART Tri-State Drivers and Buses SystemVerilog vs. Verilog

• Format: Paperback
• Language: English
• ISBN: B0D9TJGJLR
• ISBN13: 9798333236616
• Release Date: July 2024
• Publisher: Independently published
• Length: 320 Pages
• Weight: 2.02 lbs.
• Dimensions: 11.0" x 0.7" x 8.5"