This book covers the key design problems of modeling, architectural tradeoffs, functional verification, timing analysis, test generation, fault simulation, design for testablility, logic synthesis, and post-synthesis verification. The author's focus is on developing, verifying, and synthesizing designs of digital circuits rather than on the Verilog language. KEY TOPICS: Some of the topics covered in this book include Digital Design Methodology, Combinational Logic, Sequential Logic Design, Logic Design with Verilog, and Programmable Logic and Storage Devices. MARKET: For professional engineers interested in learning Verilog by example, in the context of its use in the design flow of modern integrated circuits.
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