A Pipelined Multi-Core MIPS Machine: Hardware Implementation and Correctness Proof

by Wolfgang J. Paul, Silvia M. Muller, Mikhail Kovalev, et al.

This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory.

The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially...

• Format: Paperback
• Language: English
• ISBN: 3319139053
• ISBN13: 9783319139050
• Release Date: December 2014
• Publisher: Springer
• Length: 352 Pages
• Weight: 1.12 lbs.
• Dimensions: 0.8" x 6.1" x 9.2"