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High-Level Synthesis Blue Book
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High-Level Synthesis Blue Book
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High-Level VLSI Synthesis
High-Level VLSI Synthesis
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219.99
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A Survey of High-Level Synthesis Systems (The Springer International...
A Survey of High-Level Synthesis Systems (The Springer International Series in Engineering and Computer Science)
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Separation Logic for High-Level Synthesis
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Separation Logic for High-Level Synthesis
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High-Level Synthesis: Introduction to Chip and System Design
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High-Level Synthesis: Introduction to Chip and System Design
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169.99
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Device-Level Modeling and Synthesis of High-Performance Pipeline ADC...
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Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs
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87.79
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SPARK:: A Parallelizing Approach to the High-Level Synthesis of Digi...
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SPARK:: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits
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High Level Synthesis of ASICs under Timing and Synchronization Const...
By , ,
High Level Synthesis of ASICs under Timing and Synchronization Constraints
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Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
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Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
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169.99
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Understanding Behavioral Synthesis: A Practical Guide to High-Level ...
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Understanding Behavioral Synthesis: A Practical Guide to High-Level Design
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169.99
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High Level Synthesis of Pipelined Datapaths
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High Level Synthesis of Pipelined Datapaths
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Domain Specific High-Level Synthesis
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Domain Specific High-Level Synthesis
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109.99
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High-Level Synthesis Hardware Trojan Attacks and Countermeasures
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High-Level Synthesis Hardware Trojan Attacks and Countermeasures
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145.00
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High-Level Modeling and Synthesis of Analog Integrated Systems (Anal...
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High-Level Modeling and Synthesis of Analog Integrated Systems (Analog Circuits and Signal Processing)
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169.99
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High-Level Modeling and Synthesis of Analog Integrated Systems
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High-Level Modeling and Synthesis of Analog Integrated Systems
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High-Level Synthesis: from Algorithm to Digital Circuit
High-Level Synthesis: from Algorithm to Digital Circuit
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109.99
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High Level Synthesis: From Algorithm To Digital Circuit
High Level Synthesis: From Algorithm To Digital Circuit
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109.99
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High-Level Synthesis for Real-Time Digital Signal Processing: The CA...
By , ,
High-Level Synthesis for Real-Time Digital Signal Processing: The CATHEDRAL-II Silicon Compiler (The International Series in Engineering and Computer Science)
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26.49
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High-Level Synthesis for Real-Time Digital Signal Processing
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High-Level Synthesis for Real-Time Digital Signal Processing
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High-level synthesis Standard Requirements
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High-level synthesis Standard Requirements
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Low Power Design with High-Level Power Estimation and Power-Aware Sy...
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Low Power Design with High-Level Power Estimation and Power-Aware Synthesis
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109.99
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Interconnect and Temperature Aware Unified Physical and High Level S...
By and
Interconnect and Temperature Aware Unified Physical and High Level Synthesis
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129.00
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High-level synthesis of synchronous pipelined circuits: A programmin...
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High-level synthesis of synchronous pipelined circuits: A programming language approach
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High-Level Synthesis Based Methodologies for Hardware Security, Trus...
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High-Level Synthesis Based Methodologies for Hardware Security, Trust and IP Protection
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123.01
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Structured Accelerator Design: Patterns for High-Level Synthesis
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Structured Accelerator Design: Patterns for High-Level Synthesis
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Automatic Custom Instruction Identification For High-level Synthesis...
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Automatic Custom Instruction Identification For High-level Synthesis
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RTM Kernel Implementation on FPGA using High Level Synthesis Tool
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RTM Kernel Implementation on FPGA using High Level Synthesis Tool
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Verification and Synthesis of Digital Circuits: High-level Synthesis...
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Verification and Synthesis of Digital Circuits: High-level Synthesis and Equivalence Checking
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Proceedings of the Seventh International Symposium on High-Level Syn...
Proceedings of the Seventh International Symposium on High-Level Synthesis: May 18-20, 1994, Niagara-On-The-Lake, Ontario, Canada
$
34.38
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High Level Synthesis of Digital Systems: For Data Path and Control d...
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High Level Synthesis of Digital Systems: For Data Path and Control dominated systems
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Guide to Computer Processor Architecture: A RISC-V Approach, with Hi...
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Guide to Computer Processor Architecture: A RISC-V Approach, with High-Level Synthesis
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Rescuing SDG 11 for a Resilient Urban Planet: SDG 11 Synthesis Repor...
Rescuing SDG 11 for a Resilient Urban Planet: SDG 11 Synthesis Report - High Level Political Forum 2023
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Improving Performance and Reducing Power with Hardware Acceleration:...
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Improving Performance and Reducing Power with Hardware Acceleration: Static Timing Analysis Based Transformations of Combinational Logic in a High Level ASIC Synthesis Flow
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50.56
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