Towards the Formal Verification of the Requirements and Design of a Processor Interface Unit

By: Nasa, National Aeronautics and Space Adm

The formal verification of the design and partial requirements for a Processor Interface Unit (PIU) using the Higher Order Logic (HOL) theorem-proving system is described. The processor interface unit is a single-chip subsystem within a fault-tolerant embedded system under development within the Boeing Defense and Space Group. It provides the opportunity to investigate the specification and verification of a real-world subsystem within a commercially-developed...

• Format: Paperback
• Language: English
• ISBN: 1730896618
• ISBN13: 9781730896613
• Release Date: January 1
• Publisher: Independently Published
• Length: 66 Pages
• Weight: 0.39 lbs.
• Dimensions: 0.1" x 8.5" x 11.0"